1. Field of the Invention
The present invention relates to the field of wireless communications, more particularly to correcting frequency errors in coherently demodulated wireless communication systems.
2. Description Of The Related Art
Explosive growth in the market for internet and intranet related applications has provided the impetus for a greater demand for fixed wireless networking services and systems. A wireless internet access system (WIAS) illustrated in FIG. 1 is composed of four major parts: (a) multiple data base stations (BS) 100(a) and 100(b) which provide wireless connectivity and gain coverage to subscriber units 102(a)-(d) of a large geographical area (for example, residential and corporate terminal equipment as illustrated in FIG. 1); (b) wireless modems 170(a)-(c) (hereinafter xe2x80x9cWMxe2x80x9d) which are connected to BS 100(a) or 100(b) via wireless links 115(a)-(c); (c) a data switching center (DSC) 125 with integrated management functions; and (d) a backbone transmission network 135 interconnecting (a)-(c) above.
As can be seen from FIG. 1, corporate terminals 102(c) and 102(d) can be, and many times are, connected to WM 170(c) via a local area network (LAN) and a wireless router or firewall (not shown). Additionally, BS 100(a) and 100(b) may communicate with DSC 125 via frame relays (not shown). Further in conventional wireless internet access systems or networks, DSC 125 is interconnected with backbone transmission network 135 by a router and/or firewall (not shown for clarity).
FIG. 2 illustrates BS 100(a) and 100(b) of FIG. 1 in an operational mode. Each BS 100(a) and 100(b) provides 360xc2x0 RF coverage on the order of several gigahertz (preferably operating in the 3.5 GHz spectrum using approximately 5 MHz wide channels), sending and receiving signals over air lines 115(a)-(c) between individual subscriber units 102(a)-(d) served by BS 100(a) and/or 102(b). More particularly, the designated geographical area of subscribers served by each BS 100(a) and 100(b) is typically called a cell 150, defined by its coverage area as shown in FIG. 2, where BS 100(a) and 100(b) are situated in designated cells 150(a) and 150(b). Within each cell 150(a) or 150(b) reside a plurality of subscribers 102(a)-(d) served by the BS 100(a) and/or 100(b) includes a plurality of access points (hereinafter xe2x80x9cAPxe2x80x9d, not shown in FIG. 1) serving as an interface between individual subscribers 102(a)-(d) of a cell 150(a)-(b) served by BS 100(a)-(b). Each access point includes receiver and transmitter circuitry of the base station for communicating with individual subscribers 102(a)-(d) within a designated cell 150(a)-(b).
A channel is the wireless link between an AP antenna and a WM antenna. There are a plurality of channels for receiving packets of information transmitted along various frequency bands, be it from an AP transmitter to WM receiver or vice versa. In either case, the WM and/or AP receiver can function in only one frequency band, and hence in only one channel, at a time. Further within the receiver circuitry of an AP and/or WM, there are several components used for synchronizing the time and frequency of an incoming packet with the receiver circuitry, so as to provide acceptable receiver performance.
As will be explained in more detail below, a synchronization as well as an equalization process is performed in the receiver for each incoming packet of information received by the receiver. Based on the synchronization process, a frequency offset estimation is calculated to account for the frequency offset which develops within the receiver during processing of the packet. As explained in co-pending U.S. patent application Ser. No. 09/XXX,XXX, entitled xe2x80x9cFREQUENCY AND TIME SYNCHRONIZATION IN SEVERE DELAY SPREAD CHANNELSxe2x80x9d and filed concurrently with the present application, a frequency offset exists because oscillators in both the transmitter and the receiver have different frequencies, although desirably they should have the same frequency. Accordingly, a frequency offset correction (hereinafter termed a stage 1 frequency offset correction algorithm) is performed in the synchronizer, and a frequency offset estimate (or phase drift (pd), as described in co-pending application 09/XXX,XXX) is generated by the synchronizer.
However this estimate is not perfectly accurate, i.e., there is some difference between the frequency offset and the frequency offset estimate (phase drift). This difference is termed a frequency offset estimate error, and should be corrected by application of a second correction, or a stage 2 frequency offset correction algorithm. Specifically, the frequency offset estimation errors affect the packet error rate (PER) performance, or probability that a transmitted packet cannot be received correctly by the receiver. For example, if the frequency offset estimate error causes a 1 degree per symbol phase drift, then after 180 symbols are processed by a receiver, all the symbol phases will be about 180 degrees off of the correct phases. This phase inaccuracy causes inaccurate and/or erroneous demodulation results, and thus packet errors.
To help understand the current implementation used for determining frequency offset estimation for channels in a wireless network and/or system, the following terms are defined. Each detected packet is divided into symbol segments allocated to various components within the receiver. For example, time symbol sequences can be allocated to a Barker detection unit, synchronizer and equalizer of a receiver. Typically each incoming packet includes in upwards of 2,000 time symbols that are processed in the various components of the receiver.
As previously discussed, to correct the frequency offset, the current implementation utilizes two frequency correction algorithms, a stage 1 frequency offset estimation algorithm and a stage 2 frequency correction algorithm. The function of the stage 1 frequency offset correction algorithm is to determine an initial frequency offset estimate (i.e., coarse frequency adjustment) for each incoming packet of information. The function of the stage 2 frequency correction algorithm is to compensate for any frequency error resulting from the stage 1 algorithm""s determination.
FIG. 3 illustrates components comprising part of a receiver typically used in a WM and/or AP of a wireless system. The current stage 1 and stage 2 frequency correction algorithms are explained with reference to FIG. 3, and depicts a part of a receiver 200 comprising a frequency synchronizing unit 215, frequency correction unit (FCU) 230, equalizer 235, adaptive frequency offset correction (AFOC) unit 240 and decision device 245.
In FIG. 3, each incoming packet is processed in Barker detection circuitry (informing the receiver of an incoming packet), and the received signal is subject to frequency synchronization in a frequency synchronizing unit 215. Any frequency offset developed between an oscillator of the receiver 200 (not shown) and the oscillator of the transmitter (AP) for example, can cause a constant phase drift between two time symbols. To account for this drift, frequency correction unit 230 receives inputs from frequency synchronizing unit 215 and an adaptive frequency offset correction unit (AFOC) 240 to determine a per-symbol phase drift. For example, frequency synchronizing unit 215 outputs an initial pd calculation which is then modified by an output from AFOC 240 for each sequentially received symbol of the packet.
Equalizer 235 processes the output of FCU 230 on a per-symbol basis to remove the effects of inter-symbol interference introduced by the channel. The output of equalizer 235, a complex number representing a symbol of the incoming packet, is fed to decision device 245. Decision device 245 maps this complex number to the closest QPSK symbol on the complex number plane, and outputs the result for subsequent decoding and/or demodulation in downstream circuitry to convert the complex symbols to ones and zeros for digital processing within the WM and/or AP.
The current stage 1 frequency correction algorithm estimates frequency offset frequency synchronizing unit 215. The stage 1 algorithm is performed within frequency synchronizing unit 215 and the stage 2 algorithm in AFOC unit 240. Frequency correction unit 230 rotates symbols in a complex plane based on inputs from both frequency synchronizing unit 215 and AFOC unit 240, to calculate phase drift. Specifically, FCU 230 rotates symbols based on pd.
However, due to the error of the stage 1 frequency estimate, some performance degradation is present, e.g., nearly 3 dB degradation for a channel 1, for example. The channel 1 model is a channel where there is only one propagation path between the transmitter and the receiver. The channel 1 model does not have any delay spread and is the most desirable channel conditions. This model is used for simulations to approximate the performance of typical channels, which are generally more likely to exhibit channel 1 model characteristics than other channel models exhibiting delay spread.
As discussed above, the stage 2 frequency correction algorithm is designed to compensate for the frequency error resulting from the stage 1 computations. The current stage 2 algorithm is effective in correcting frequency errors up to about 0.6 degree per symbol without substantial degradation. The stage 2 algorithm has two parameters: a frequency increment (FI) amount and a counter threshold (CT), which equal to 0.05xc2x0/symbol and 4 respectively from current simulations used to perfect the algorithm. As noted above, the stage 2 algorithm is performed in AFOC unit 240. AFOC unit 240 compares the phase of a symbol output from equalizer 235 and the phase of the same symbol output from decision device 245. If the phase of 235 output is larger than that of 245 output, CT is decremented (decreased). Otherwise, CT is incremented [increased] for each symbol, up to a counter threshold of xc2x14. More particularly, this frequency correction is applied when the absolute value of the counter reaches 4, whereupon CT is then reset to zero again. Once CT=xc2x14, a fixed amount of frequency correction (xc2x10.05). For example, if CT=4, +0.05 is applied; if CT=xe2x88x924, xe2x88x920.05 is applied to the frequency estimate determined by the stage 1 algorithm in frequency synchronizing unit 215.
To illustrate this, consider x as the phase of a symbol output from equalizer 235, and y to be the phase of the same symbol, but output of decision device 245. If x less than y, the counter CT increments (increases by +1). However, if x greater than y, the counter decrements by xe2x88x921. The values x and y are actually complex numbers which represent the phases. Thus, if the counter reaches |xc2x14|, FCU 230 alters the per symbol phase drift amount PD by xc2x10.05xc2x0 for that symbol. For example, if CT=+4 at the threshold, this means that the phases of the equalizer 235 x outputs are generally smaller (lagging) the phases of the HDD 245 y outputs. Since x and y are complex numbers, the process of increasing the phase of a complex number can be visually analogous to rotating a complex number (of the phase) counterclockwise on a complex plane. Likewise, decreasing the phase of a complex number is like rotating it clockwise.
Accordingly, when CT=+4 in this example, what is desired is to add more degrees to the phase of the equalizer 235 inputs, so as to increase the per-symbol phase drift amount stored in FCU 230 by +0.050. Conversely, if the counter value CT reaches xe2x88x924, the phases of the equalizer inputs need to be reduced, so as to decrease the per symbol phase drift (pd) by xe2x88x920.05xc2x0.
Although the current stage 2 algorithm is effective in correcting frequency errors up to 0.6 degree per symbol, the performance degradation for the channel 1 model (in this example) becomes much more obvious when the frequency offset correction required is greater than 0.8xc2x0 per symbol, i.e., signifying large frequency errors. Further, since channel 1 operates at a lower signal-to-noise ratio (Es/No=15 dB) than some of the other channels in the wireless communication system, the estimated root means square (RMS) of the frequency error for channel 1 is typically greater than 0.6xc2x0 per symbol. This means that there is a large performance loss (in terms of PER) for channel 1 due to frequency offset estimate errors. This is because the current stage 2 algorithm is ineffective in correcting these much larger frequency errors, which results in nearly 3 dB degradation due to the inaccuracy of the stage 1 frequency estimate. Accordingly, what is needed is a method which improves the frequency correction performance of the stage 2 algorithm, thereby combating the larger frequency errors while still maintaining the ability to handle and process small frequency errors.
The present invention provides a method for correcting frequency errors in a receiver of a coherent demodulated wireless communication system. The method comprises performing a first count for a plurality of sequential symbols of a transmitted packet up to a threshold; performing a second count for said plurality of symbols; and applying a frequency correction which is a function of said first and second counts. Additionally, the method adjusts the size of the frequency correction applied to the receiver to combat frequency errors which are generally larger at the beginning of an incoming packet, and which decrease for the remainder of the symbols of the packet processed in the receiver.